256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354BV25 and C

文件：518.37 Kbytes 页数：27 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354BV25 and C

文件：518.37 Kbytes 页数：27 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354BV25 and C

文件：518.37 Kbytes 页数：27 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354BV25 and C

文件：518.37 Kbytes 页数：27 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司