256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture

Functional Description The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells,

文件：563.4 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture

Functional Description The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells,

文件：563.4 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture

Functional Description The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells,

文件：563.4 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture

Functional Description The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells,

文件：563.4 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司