256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

文件：402.54 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

文件：402.54 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

文件：402.54 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

文件：402.54 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

文件：402.54 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

文件：402.54 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture

Infineon

英飞凌

256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture

Functional Description\nThe CY7C1354A and CY7C1356A SRAMs are designed to eliminate dead cycles when transitioning from Read to Write or vice versa. These SRAMs are optimized for 100% bus utilization and achieve Zero Bus Latency™ (ZBL™)/No Bus Latency™ (NoBL™). They integrate 262,144 × 36 and 52 • Zero Bus Latency™, no dead cycles between Write and Read cycles\n• Fast access time: 3.2, 3.6, 4.2, 5.0 ns\n• Single 3.3V –5% and +5% power supply VCC\n• Single WEN (Read/Write) control pin\n• Interleaved or linear four-word burst capability\n• CEN pin to enable clock and suspend operation;

Infineon

英飞凌