4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1348G SRAM integrates 128K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • Reg

文件：348.31 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1348G SRAM integrates 128K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • Reg

文件：348.31 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1348G SRAM integrates 128K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • Reg

文件：348.31 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1348G SRAM integrates 128K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • Reg

文件：348.31 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1348G SRAM integrates 128K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • Reg

文件：348.31 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1348G SRAM integrates 128K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • Reg

文件：348.31 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1348G SRAM integrates 128K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • Reg

文件：348.31 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1348G SRAM integrates 128K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • Reg

文件：348.31 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1348G SRAM integrates 128K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • Reg

文件：348.31 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Infineon

英飞凌