4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

文件：1.02152 Mbytes 页数：21 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

文件：1.02152 Mbytes 页数：21 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

文件：1.02152 Mbytes 页数：21 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K x 36) Pipelined Sync SRAM Asynchronous output enable

文件：808.8 Kbytes 页数：24 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K 횞 36) Pipelined Sync SRAM

文件：538.13 Kbytes 页数：25 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司