2-Mbit (64K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1346F SRAM integrates 65,536 x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • R

文件：321.76 Kbytes 页数：16 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (64K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1346F SRAM integrates 65,536 x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • R

文件：321.76 Kbytes 页数：16 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (64K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1346F SRAM integrates 65,536 x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • R

文件：321.76 Kbytes 页数：16 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (64K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1346F SRAM integrates 65,536 x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • R

文件：321.76 Kbytes 页数：16 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (64K x 36) Pipelined Sync SRAM

Infineon

英飞凌