CY7C1345B中文资料赛普拉斯数据手册PDF规格书

Functional Description

The CY7C1345B is a 3.3V, 128K by 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features

• Supports 117-MHz microprocessor cache systems with

zero wait states

• 128K by 36 common I/O

• Fast clock-to-output times

— 7.5 ns (117-MHz version)

• Two-bit wrap-around counter supporting either

interleaved or linear burst sequence

• Separate processor and controller address strobes

provide direct interface with the processor and external

cache controller

• Synchronous self-timed write

• Asynchronous output enable

• Supports 3.3V & 2.5V I/O levels

• ZZ “sleep” mode