128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

文件：600.16 Kbytes 页数：18 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

文件：600.16 Kbytes 页数：18 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

Package：100-LQFP；包装：管件 类别：集成电路（IC） 存储器 描述：IC SRAM 4MBIT PARALLEL 100TQFP

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

文件：600.16 Kbytes 页数：18 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

文件：600.16 Kbytes 页数：18 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司