CY7C133-55JC中文资料赛普拉斯数据手册PDF规格书

Functional Description

The CY7C133 and CY7C143 are high-speed CMOS 2K by 16 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C133 can be utilized as either a stand-alone 16-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C143 slave dual-port device in systems requiring 32-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.

特性 Features

• True dual-ported memory cells which allow simultaneous reads of the same memory location

• 2K x 16 organization

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 25/35/55 ns

• Low operating power: ICC = 150 mA (typ.)

• Fully asynchronous operation

• Master CY7C133 expands data bus width to 32 bits or more using slave CY7C143

• BUSY output flag on CY7C133; BUSY input flag on CY7C143

• Available in 68-pin PLCC