2-Mbit (128K x 18) Pipelined Sync SRAM

Functional Description[1] The CY7C1326H SRAM integrates 128K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • 128K × 18 common I/O architecture • 3.3V core powe

文件：678.05 Kbytes 页数：15 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (128K x 18) Pipelined Sync SRAM

Functional Description[1] The CY7C1326H SRAM integrates 128K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • 128K × 18 common I/O architecture • 3.3V core powe

文件：678.05 Kbytes 页数：15 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (128K x 18) Pipelined Sync SRAM

Functional Description[1] The CY7C1326H SRAM integrates 128K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • 128K × 18 common I/O architecture • 3.3V core powe

文件：678.05 Kbytes 页数：15 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (128K x 18) Pipelined Sync SRAM

Functional Description[1] The CY7C1326H SRAM integrates 128K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • 128K × 18 common I/O architecture • 3.3V core powe

文件：678.05 Kbytes 页数：15 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2-Mbit (128K x 18) Pipelined Sync SRAM

Functional Description[1] The CY7C1326H SRAM integrates 128K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • 128K × 18 common I/O architecture • 3.3V core powe

文件：678.05 Kbytes 页数：15 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司