18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Features • 18-Mb density (2M x 8, 1M x 18, 512K

文件：228.92 Kbytes 页数：20 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Infineon

英飞凌

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Features • 18-Mb density (2M x 8, 1M x 18, 512K

文件：228.92 Kbytes 页数：20 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Features • 18-Mb density (2M x 8, 1M x 18, 512K

文件：228.92 Kbytes 页数：20 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Features • 18-Mb density (2M x 8, 1M x 18, 512K

文件：228.92 Kbytes 页数：20 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司