Errata Document for CY7C1312V18 & CY7C1314V18

Functional Description The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri

文件：47.58 Kbytes 页数：5 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

Errata Document for CY7C1312V18 & CY7C1314V18

Functional Description The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri

文件：47.58 Kbytes 页数：5 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

Errata Document for CY7C1312V18 & CY7C1314V18

Functional Description The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri

文件：47.58 Kbytes 页数：5 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

PLCC52

CYPRESS/赛普拉斯

上传：深圳市大联智电子有限公司

100TQFP

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

上传：深圳市宏世佳电子科技有限公司