1-Mbit (32K x 36) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1219F SRAM integrates 32,768 x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

文件：333.23 Kbytes 页数：15 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

1-Mbit (32K x 36) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1219F SRAM integrates 32,768 x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

文件：333.23 Kbytes 页数：15 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

1-Mbit (32K x 36) Pipelined DCD Sync SRAM

Infineon

英飞凌

1-Mbit (32K x 36) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1219H SRAM integrates 32K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

文件：359.99 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司