1-Mbit (64K x 18) Pipelined Sync SRAM

Functional Description[1] The CY7C1212F SRAM integrates 65,536 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • 64K × 18 common I/O architecture • 3.3V core pow

文件：318.06 Kbytes 页数：15 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

1-Mbit (64K x 18) Pipelined Sync SRAM

Functional Description[1] The CY7C1212F SRAM integrates 65,536 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • 64K × 18 common I/O architecture • 3.3V core pow

文件：318.06 Kbytes 页数：15 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

1-Mbit (64K x 18) Pipelined Sync SRAM

Infineon

英飞凌

1-Mbit (64K x 18) Pipelined Sync SRAM

Functional Description[1] The CY7C1212H SRAM integrates 64K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous i

文件：353.28 Kbytes 页数：15 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司