18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

Functional Description The CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read o

文件：1.16229 Mbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

Functional Description The CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read o

文件：1.16229 Mbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

Functional Description The CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read o

文件：1.16229 Mbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

Functional Description The CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read o

文件：1.16229 Mbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

Functional Description The CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read o

文件：1.16229 Mbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司