CY7C1156V18

18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

FunctionalDescription TheCY7C1141V18,CY7C1156V18,CY7C1143V18,andCY7C1145V18are1.8VSynchronousPipelinedSRAMs,equippedwithQDR™-II+architecture.QDR-II+architectureconsistsoftwoseparateportstoaccessthememoryarray.Thereadporthasdedicateddataoutputstosupportreado

CY7C1156V18-300BZC

18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

FunctionalDescription TheCY7C1141V18,CY7C1156V18,CY7C1143V18,andCY7C1145V18are1.8VSynchronousPipelinedSRAMs,equippedwithQDR™-II+architecture.QDR-II+architectureconsistsoftwoseparateportstoaccessthememoryarray.Thereadporthasdedicateddataoutputstosupportreado

CY7C1156V18-300BZI

18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

FunctionalDescription TheCY7C1141V18,CY7C1156V18,CY7C1143V18,andCY7C1145V18are1.8VSynchronousPipelinedSRAMs,equippedwithQDR™-II+architecture.QDR-II+architectureconsistsoftwoseparateportstoaccessthememoryarray.Thereadporthasdedicateddataoutputstosupportreado

CY7C1156V18-300BZXC

18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

FunctionalDescription TheCY7C1141V18,CY7C1156V18,CY7C1143V18,andCY7C1145V18are1.8VSynchronousPipelinedSRAMs,equippedwithQDR™-II+architecture.QDR-II+architectureconsistsoftwoseparateportstoaccessthememoryarray.Thereadporthasdedicateddataoutputstosupportreado

CY7C1156V18-300BZXI

18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

FunctionalDescription TheCY7C1141V18,CY7C1156V18,CY7C1143V18,andCY7C1145V18are1.8VSynchronousPipelinedSRAMs,equippedwithQDR™-II+architecture.QDR-II+architectureconsistsoftwoseparateportstoaccessthememoryarray.Thereadporthasdedicateddataoutputstosupportreado