Features

■ True dual-ported memory cells which enable simultaneous access of the same memory location

■ 4, 8 or 16K × 16 organization

■ (CY7C024AV/024BV [1]/ 025AV/026AV)

■ 4 or 8K × 18 organization (CY7C0241AV/0251AV)

■ 16K × 18 organization (CY7C036AV)

■ 0.35 micron CMOS for optimum speed and power

■ High speed access: 20 and 25 ns

■ Low operating power

❐ Active: ICC = 115 mA (typical)

❐ Standby: ISB3 = 10 μA (typical)

■ Fully asynchronous operation

■ Automatic power down

■ Expandable data bus to 32 bits, 36 bits or more using Master and Slave chip select when using more than one device

■ On chip arbitration logic

■ Semaphores included to permit software handshaking between ports

■ INT flag for port-to-port communication

■ Separate upper byte and lower byte control

■ Pin select for Master or Slave (M/S)

■ Commercial and industrial temperature ranges

■ Available in 100-pin Pb-free TQFP and 100-pin TQFP