CY7C009V中文资料赛普拉斯数据手册PDF规格书

Functional Description

The CY7C008V/009V and CY7018V/019V are low-power CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory.

特性 Features

• True Dual-Ported memory cells which allow simultaneous access of the same memory location

• 64K x 8 organization (CY7C008)

• 128K x 8 organization (CY7C009)

• 64K x 9 organization (CY7C018)

• 128K x 9 organization (CY7C019)

• 0.35-micron CMOS for optimum speed/power

• High-speed access: 15/20/25 ns

• Low operating power

— Active: ICC = 115 mA (typical)

— Standby: ISB3 = 10 µA (typical)

• Fully asynchronous operation

• Automatic power-down

• Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device

• On-chip arbitration logic

• Semaphores included to permit software handshaking between ports

• INT flag for port-to-port communication

• Dual Chip Enables

• Pin select for Master or Slave

• Commercial and Industrial Temperature Ranges

• Available in 100-pin TQFP

• Pb-Free packages available