CY7B9910集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Functional Description

The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low skew system clock distribution. These multiple output clock drivers optimize the timing of high performance computer systems. Each of the eight individual drivers can drive terminated transmission lines with impedances as low as 50Ω. They deliver minimal and specified output skews and full swing logic levels (CY7B9910 TTL or CY7B9920 CMOS).

Features

■ All outputs skew <100 ps typical (250 max.)

■ 15 to 80 MHz output operation

■ Zero input to output delay

■ 50 duty cycle outputs

■ Outputs drive 50Ω terminated lines

■ Low operating current

■ 24-pin SOIC package

■ Jitter: