CY74FCT273TSOC集成电路（IC）的触发器规格书PDF中文资料

CY74FCT273TSOC属于集成电路（IC）的触发器。由美国德州仪器公司制造生产的CY74FCT273TSOC触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。

Function, Pinout, and Drive Compatible

With FCT and F Logic

Reduced VOH (Typically = 3.3 V) Versions

of Equivalent FCT Functions

Edge-Rate Control Circuitry for

Significantly Improved Noise

Characteristics

Ioff Supports Partial-Power-Down Mode

Operation

Matched Rise and Fall Times

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

Fully Compatible With TTL Input and

Output Logic Levels

CY54FCT273T

– 32-mA Output Sink Current

– 12-mA Output Source Current

CY74FCT273T

– 64-mA Output Sink Current

– 32-mA Output Source Current

description

The ’FCT273T devices consist of eight

edge-triggered D-type flip-flops with individual

D inputs and Q outputs. The common

buffered-clock (CP) and master-reset (MR) inputs

load and reset all flip-flops simultaneously. These

devices are edge-triggered registers. The state of

each D input (one setup time before the

low-to-high clock transition) is transferred to the

corresponding flip-flop’s Q output. All outputs are

forced low by a low logic level on the MR input.

This device is fully specified for

partial-power-down applications using Ioff. The Ioff

circuitry disables the outputs, preventing

damaging current backflow through the device

when it is powered down.