CY54FCT480T中文资料双路 8 位奇偶校验生成器/校验器数据手册TI规格书

描述 Description

The \\x92FCT480T devices are high-speed, dual, 8-bit parity generators/checkers. Each parity generator/checker accepts eight data bits and one parity bit as inputs, and generates a sum and parity-error (ERROR\\) output. These devices can be used in odd-parity systems. ERROR\\ is an open-drain output designed for easy expansion of the word width by a wired-OR connection of several \\x92FCT480T devices. Because no additional logic is needed, the parity-generation or parity-checking times remain the same as for an individual \\x92FCT480T device. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性 Features

• Function, Pinout, and Drive Compatible With FCT and F Logic
• Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
• Matched Rise and Fall Times
• Two 8-Bit Parity Generators/Checkers
• Expandable for Larger Word Widths
• 200-V Machine Model (A115-A)
• CY54FCT480T
• 12-mA Output Source Current
• 32-mA Output Source Current