CY2309SC-1集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Functional Description

The CY2309 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low-skew clocks. The -1H versions of each device operate at up to 100-/133-MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

特性 Features

• 10-MHz to 100-/133-MHz operating range, compatible with CPU and PCI bus frequencies

• Zero input-output propagation delay

• 60 ps typical cycle-to-cycle jitter (high drive)

• Multiple low-skew outputs

— 85 ps typical output-to-output skew

— One input drives five outputs (CY2305)

— One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)

• Compatible with Pentium-based systems

• Test Mode to bypass phase-locked loop (PLL) (CY2309 only [see “Select Input Decoding” on page 2])

• Available in space-saving 16-pin 150-mil SOIC or 4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil SOIC package (CY2305)

• 3.3V operation

• Industrial temperature available