CY2213集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

CY2213属于集成电路（IC）的时钟发生器PLL频率合成器。由赛普拉斯半导体公司制造生产的CY2213时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。

Introduction

The CY2213 has a two-wire serial interface designed for data transfer operations, and is used for programming the P and Q values for frequency generation. Sclk is the serial clock line controlled by the master device. Sdata is a serial bidirectional data line. The CY2213 is a slave device and can either read or write information on the dataline upon request from the master device.

特性 Features

• Jitter peak-peak (TYPICAL) = 35 ps

• LVPECL output

• Default Select option

• Serially-configurable multiply ratios

• Output edge-rate control

• 16-pin TSSOP

• High frequency

• 3.3V operation

Benefits

High-accuracy clock generation

One pair of differential output drivers

Phase-locked loop (PLL) multiplier select

Eight-bit feedback counter and six-bit reference counter for high accuracy

Minimize electromagnetic interference (EMI)

Industry-standard, low-cost package saves on board space

125- to 400-MHz (-1) or to 500-MHz (-2) extended output range for high-speed applications

Enables application compatibility