CXL5005M中文资料CMOS-CCD 1H Delay Line for NTSC with PLL数据手册Sony规格书

描述 Description

The CXL5005M/P are general-purpose CCD delay line ICs which provide 1H delay time of NTSC.

特性 Features

• Low power consumption 90mW (Typ.)
• Small size package (14-pin SOP, DIP)
• Low differential gain DG = 3% (Typ.)
• Input signal ampiitude 180 IRE (= 1.28Vp-p, max.)
• Low input clock amplitude operation 200mVp-p (Min.)
• Built-in triple PLL circuit
• Built-in peripheral circuits (clock driver, timing generator, auto-bias and output circuits)Functions
• 680-bit CCD register
• Clock drivers
• Autobias circuit
• Sync tip clamp circuit
• Sample-and-hold circuit
• PLL (triple)