CXL5002P中文资料索尼数据手册PDF规格书

Description

The CXL5002M/P are general-purpose CMOS-CCD delay line ICs that provide 1/2H delay time for NTSC.

Features

• Low power consumption 70mW (Typ.)

• Small size package (8-pin SOP, DIP)

• Low differential gain DG = 3 (Typ.)

• Input signal amplitude 180 IRE (= 1.28Vp-p, Max.)

• Low input clock amplitude operation 150mVp-p (Min.)

• Built-in peripheral circuits (clock driver, timing generator, autobias, and output circuits)

Functions

• 340-bit CCD register

• Clock drivers

• Autobias circuit

• Sync tip clamp circuit

• Sample and hold circuit