CX24254-24UZ中文资料SD MPEG-2 SoC with DVR数据手册恩XP规格书

描述 Description

OverviewThe CX2425x family offers an MPEG®-2 MP@ML decoder (Dolby Digital audio is optional), multiple transport stream inputs, a transport processor, a 32-bit RISC CPU, a 2D graphics accelerator, a TV encoder, a channel 3/4 RF modulator, a video/graphics display compositing controller, and a set of peripheral I/O ports for set-top box (STB) front and back panel connectors.

特性 Features

•MPEG®-2/DVB/DIRECTV broadcast service decoder for worldwide markets

•Basic SDTV DVR solution with dual input, single output

•High-performance 32-bit 275 MIPS ARM926 CPU with 16KB I and D caches

•Advanced security features, including secure boot software authentication, IC personalization via OTP memory, and 3DES/AES ciphering engines

•Glueless interface to MPEG-4 AVC/H.264 coprocessor

•High-performance peripheral I/O, including dual USB 2.0, high speed UART, and SATA HDD support

•High-performance 8- or 16-bit DDR-SDRAM memory controller architecture

•656 YCrCb and I²S I/O