CSD965200VBRR中文资料德州仪器数据手册PDF规格书

1 Features

• 100A peak current capability

• Thermally Enhanced Package (TEP)

• RθJC (top) < 0.4°C/W

• Reduced switch-node ringing

• Integrated clamping circuitry for avalanche free

operation

• High-frequency operation (up to 2MHz)

• Temperature compensated bi-directional current

sense with current mode reporting (5μA/A)

• Native TLVR support

• Body braking mode (BB)

• Forced continuous conduction mode (FCCM)

operation

• Diode Emulation Mode (DEM)

• 4mm x 6mm QFN industry common footprint

package

• Green, RoHS compliant without exemption

• Limp Mode Fault Reporting

– TAO and IOUT signal handshaking scheme to

report specific fault to controller

• Fault detection

– High-side short (HSS)

• Fault protection

– Over temperature (OT)

– Cycle-by-cycle negative over current limiting

(NOC)

– High-Side and Low-Side positive over current

protection

– BOOT UVLO

2 Applications

• Data center & enterprise computing rack server

• Hardware accelerator

• Network interface card (NIC)

• ASIC and high performance client

• ASIC power for networking and communications

• High phase count buck regulator solutions

3 Description

The CSD965200 power stage is a highly optimized

design for use in a high-power, high-density

synchronous buck converter. This product integrates

the driver IC and power MOSFETs into one Pbfree

monolithic design to complete the power stage

switching function. There are VIN bypass capacitors

integrated into the package for minimum loop

inductance and improved ringing. This combination

produces high-current, high-efficiency, and high-speed

switching capability in a small industry standard 4mm

x 6mm footprint.

Furthermore, CSD965200 is built with a Thermally

Enhanced Package (TEP) using additional top side

cooling for improved heat dissipation. TEP yields

performance benefit, especially at high load currents.

CSD965200 integrates accurate current sensing and

temperature sensing functionality to simplify system

design and improve accuracy. This power stage

also includes cycle-by-cycle current limiting and

protection based on HS FET current sense, HS FET

short and over temperature detection and protection,

negative over current detection, open pin detection,

handshaking and system diagnosis when paired with

the TPS536xx and TPS537xx series controllers.