CS4207集成电路（IC）的编解码器规格书PDF中文资料

CS4207属于集成电路（IC）的编解码器。由凌云逻辑制造生产的CS4207编解码器编解码器是用于通过压缩和解压缩来转换数据的半导体器件。数据压缩可提高传输速度并减少存储空间。某些编解码器提供高达 32 位的分辨率，并且分别提供多达 6 个或 8 个模数转换器和数模转换器。除三角积分调制外，还有 I2C、I2S、SPI、串行、HDA、S/DIF、PCM、USB、AC'97 和 SLIMbus 数据接口。

General Description

The CS4207 is a highly integrated multi-channel low power HD Audio Codec featuring 192 kHz DACs, 96 kHz ADCs, 192 kHz S/PDIFTransmitters and Receiver, Microphone pre-amp and bias voltage, and a ground centered Headphone driver. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 32 kHz and 192 kHz.

DIGITAL to ANALOG FEATURES

DAC1 (Headphone)

– 101 dB Dynamic Range (A-wtd)

– -89 dB THD+N

Headphone Amplifier - GND Centered

– Integrated Negative-voltage Regulator

– No DC-blocking Capacitor Required

– 50 mW Power/Channel into 16

DAC2 & DAC3 (Line Outs)

– 110 dB Dynamic Range (A-wtd)

– -94 dB THD+N

– Differential Balanced or Single-ended

Each DAC Supports 32 kHz to 192 kHz Sample Rates Independently.

Digital Volume Control

– +6.0 dB to -57.5 dB in 0.5 dB Steps

– Zero Cross and/or Soft Ramp Transitions

Independent Support of D0 and D3 Power States for Each DAC

Fast D3 to D0 Transition

– Audio Playback in Less Than 50 ms

ANALOG to DIGITAL FEATURES

ADC1 & ADC2

– 105 dB Dynamic Range (A-wtd)

– -88 dB THD+N

– Differential Balanced or Single-ended Inputs

– Analog Programmable Gain Amplifier (PGA) ±12 dB, 1.0 dB Steps, with Zero Cross Transitions and Mute

MIC Inputs

– Pre-amplifier with Selectable 0 dB, +10 dB, +20 dB, and +30 dB Gain Settings

– Programmable, Low-noise MIC Bias Level

Each ADC Supports 8 kHz to 96 kHz Sample Rates Independently

Additional Digital Attenuation Control

– -13.0 dB to -51.0 dB in 1.0 dB steps

– Zero Cross and/or Soft Ramp Transitions

Digital Interface for Two Dual Digital Mic Inputs

Independent Support of D0 and D3 Power States for Each ADC

System Features

Very Low D3 Power Dissipation of <7 mW

– Jack Detect Active in D3

– HDA BITCLK Not Required for D3 State

Jack Detect Does Not Require HDA Bus BITCLK

All Configuration Settings are Preserved in D3 State

Pop/Click Suppression in State Transitions

Detects Wake Event and Generates Power State Change Request when HDA Bus Controller is in D3

Variable Power Supplies

– 1.5 V to 1.8 V Digital Core Voltage

– 3.3 V to 5.0 V Analog Core Voltage

– 3.3 V to 5.0 V Headphone Drivers

– 1.5 V to 3.3 V HD Bus Interface Logic

– 3.3 V Interface Logic levels for GPIO, S/PDIF, and Digital Mic

Individual Power-down Managed

– ADCs, DACs, PGAs, Headphone Driver, S/PDIF Receiver, and Transmitters