Fractional-N Clock Multiplier

General Description The CS2100-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-CP is based on a hybrid ana log-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digita

文件：412.58 Kbytes 页数：32 Pages

CIRRUS

凌云逻辑

Fractional-N Clock Multiplier

General Description The CS2100-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-CP is based on a hybrid ana log-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digita

文件：412.58 Kbytes 页数：32 Pages

CIRRUS

凌云逻辑

Fractional-N Clock Multiplier

General Description The CS2100-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-CP is based on a hybrid ana log-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digita

文件：412.58 Kbytes 页数：32 Pages

CIRRUS

凌云逻辑

Fractional-N Clock Multiplier

General Description The CS2100-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital

文件：542.19 Kbytes 页数：28 Pages

CIRRUS

凌云逻辑

Fractional-N Clock Multiplier

General Description The CS2100-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital

文件：542.19 Kbytes 页数：28 Pages

CIRRUS

凌云逻辑

Fractional-N Clock Multiplier

General Description The CS2100-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital

文件：542.19 Kbytes 页数：28 Pages

CIRRUS

凌云逻辑

Fractional-N Clock Multiplier

文件：278.56 Kbytes 页数：32 Pages

CIRRUS

凌云逻辑

Fractional-N Clock Multiplier

文件：278.56 Kbytes 页数：32 Pages

CIRRUS

凌云逻辑

Fractional-N Clock Multiplier

文件：278.56 Kbytes 页数：32 Pages

CIRRUS

凌云逻辑

Fractional-N Clock Multiplier

文件：278.56 Kbytes 页数：32 Pages

CIRRUS

凌云逻辑