CLVC2G74QDCURG4Q1集成电路（IC）的触发器规格书PDF中文资料

CLVC2G74QDCURG4Q1属于集成电路（IC）的触发器。由德州仪器制造生产的CLVC2G74QDCURG4Q1触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。

1FEATURES

· Qualified for Automotive Applications

· Supports 5-V VCC Operation

· Inputs Accept Voltages to 5.5 V

· Max tpd of 6.9 ns at 3.3 V

· Low Power Consumption, 10-mA Max ICC

· ±24-mA Output Drive at 3.3 V

· Typical VOLP (Output Ground Bounce) <0.8 V at

VCC = 3.3 V, TA = 25°C

· Typical VOHV (Output VOH Undershoot) >2 V at

VCC = 3.3 V, TA = 25°C

· Ioff Supports Partial-Power-Down Mode

Operation

· Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.