SILICON PLANAR EPITAXIAL TRANSISTORS

文件：126.23 Kbytes 页数：5 Pages

CDIL

SILICON PLANAR EPITAXIAL TRANSISTORS

CDIL

Small Signal MOSFET Transistor P-Channel Enhancement-Mode Transistor Chip

PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 21.7 x 17.7 MILS Die Thickness 5.5 MILS Gate Bonding Pad Area 4.7 x 4.7 MILS Source Bonding Pad Area 6.1 x 7.9 MILS Top Side Metalization Al-Si - 35,000Å Back Side Metalization Au - 12,000Å

文件：704.37 Kbytes 页数：2 Pages

Central

EPITAXIAL PLANAR SILICON TRANSISTORS

文件：718 Kbytes 页数：4 Pages

CDIL

EPITAXIAL PLANAR SILICON TRANSISTORS

文件：718 Kbytes 页数：4 Pages

CDIL