CH7517数据手册Chrontel中文资料规格书

描述 Description

Chrontel's CH7517 is a low-cost, low-power semiconductor device that translates the DisplayPort signal to the VGA. This innovative DisplayPort receiver with an integrated VGA encoder is specially designed to target the notebook/ultrabook, tablet device and PC market segments. Through the CH7517's advanced decoding / encoding algorithm, the input DisplayPort high-speed serialized multimedia data can be seamlessly converted to analog RGB video output.

The CH7517 is compliant with the DisplayPort specification version 1.2 and the Embedded DisplayPort Specification version 1.3. In the device's receiver block, which supports two DisplayPort Main Link Lanes input with data rate running at either 1.62Gb/s or 2.7Gb/s, can accept RGB digital formats in either 18-bit 6:6:6 or 24-bit 8:8:8, and converted the input signal to VGA output up to 1920x1200@60Hz or 2048x1152@60Hz with reduced blanking. Leveraging the DisplayPort's unique source/sink “Link Training” routine, the CH7517 is capable of instantly bring up the video display to the VGA monitor when the initialization process is completed between CH7517 and the graphic chip.

The DACs are based on current source architecture. And the VGA output meet VESA VSIS v1r2 clock jitter target. With sophisticated MCU and the on-chip Flash, CH7517 support auto-boot and EDID buffer. After the configuration by firmware, which is auto loaded from the Flash embedded, CH7517 supports DisplayPort input detection, DAC connection detection and determine to enter into Power saving mode automatically.

特性 Features

·Compliant with DisplayPort specification version 1.2 and Embedded DisplayPort (eDP) specification version 1.3.\r
·Support 2 Main Link Lanes at either 1.62Gb/s or 2.7Gb/s link rate\r
·Support analog RGB output for VGA with Triple 9-bit DAC up to 200MHz pixel rate. Sync signals can be provided in separated or composite manner. Support VESA and CEA timing standards up to 1920x1200@60Hz or 2048x1152@60Hz with reduced blanking\r
·VGA output is compliant with VESA VSIS v1r2 specification\r
·Embedded MCU to handle the control logic\r
·Support device boot up by automatically loading firmware from on-chip flash Boot ROM\r
·Integrated EDID Buffer, and MCCS bypass supported\r
·Supports Enhanced Framing Mode\r
·Fast and full Link Training for embedded DisplayPort system\r
·Support eDP Authentication: Alternative Scramble Seed Reset and Alternative Framing\r
·2 work modes: connect 27MHz crystal, inject 27MHz clock\r
·DAC connection detection supported\r
·DP input detection supported\r
·Support Auto Power Saving mode and low stand-by current\r
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