CDCVF310PW集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

CDCVF310PW属于集成电路（IC）的时钟缓冲器驱动器。由德州仪器制造生产的CDCVF310PW时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。

1FEATURES

· High-Performance 1:10 Clock Driver

· Pin-to-Pin Skew < 100 ps at VDD 3.3 V

· VDD Range = 2.3 V to 3.6 V

· Input Clock Up To 200 MHz (See Figure 7)

· Operating Temperature Range –40°C to 85°C

· Output Enable Glitch Suppression

· Distributes One Clock Input to Two Banks of

Five Outputs

· Packaged in 24-Pin TSSOP

· Pin-to-Pin Compatible to the CDCVF2310,

Except the R = 22-Ω Series Damping

Resistors at Yn

APPLICATIONS

· General-Purpose Applications

DESCRIPTION

The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five

outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless

of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a

low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on

the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins

(1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a

2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable

sequence to distribute full period clock signals.

The CDCVF310 is characterized for operation from –40C to 85C.