CDCVF25081D集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

CDCVF25081D属于集成电路（IC）的时钟发生器PLL频率合成器。由德州仪器制造生产的CDCVF25081D时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。

1 Features

• Phase-locked loop based, zero-delay buffer

– 1 clock input to 2 banks of 4 outputs

– No external RC network required

• Supply voltage: 3 V to 3.6 V

• Operating frequency: 8 MHz to 200 MHz

• Low additive jitter (cycle-cycle): ±100 ps for

66 MHz to 200 MHz

• Power-down mode available

– Current consumption: < 20 μA in

Power-down mode

• 25-Ω on-chip series damping resistors

• Industrial temperature range: –40°C to 85°C

• Spread Spectrum Clock Compatible (SSC)

• Packaged in

– 9.9-mm × 3.91-mm, 16-pin SOIC (D)

– 5.0-mm × 4.4-mm, 16-pin TSSOP (PW)

2 Applications

• Defense radio

• Production switchers and mixers

• Radar

• In-vitro diagnostics

• CT & PET scanner

3 Description

The CDCVF25081 is a high performance, low skew,

low jitter, phased-locked loop clock driver. It uses a

PLL to precisely align, in both frequency and phase,

the output clocks to the input clock signal. The outputs

are divided into 2 banks for a total of 8 buffered

CLKIN outputs. The device automatically puts the

outputs to a low state when no CLKIN signal is

present (power down mode).

The S1 and S2 pins allow selection between PLL or

bypassed PLL outputs. When left open, the outputs

are disabled to a logic low state.

The part supports a fail-safe function. The device

further incorporates an input hysteresis which

prevents random oscillation of the outputs in the

absence of an input signal.

The device operates in 3.3V supply environment

and is characterized from –40°C to 85°C (ambient

temperature).