CDCLVP111VF集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

CDCLVP111VF属于集成电路（IC）的时钟缓冲器驱动器。由德州仪器制造生产的CDCLVP111VF时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。

1 Features

1• Distributes One Differential Clock Input Pair

LVPECL to 10 Differential LVPECL

• Fully Compatible With LVECL and LVPECL

• Supports a Wide Supply Voltage Range from

2.375 V to 3.8 V

• Selectable Clock Input Through CLK_SEL

• Low-Output Skew (Typical 15 ps) for Clock-

Distribution Applications

– Additive Jitter Less Than 1 ps

– Propagation Delay Less Than 350 ps

– Open Input Default State single–

LVDS, CML, SSTL Input Compatible

• VBB Reference Voltage Output for Single-Ended

Clocking

• Available in a 32-Pin LQFP and QFN Package

• Frequency Range From DC to 3.5 GHz

• Pin-to-Pin Compatible With MC100 Series EP111,

ES6111, LVEP111, PTN1111

2 Applications

• Designed for Driving 50-Ω Transmission Lines

• High Performance Clock Distribution

3 Description

The CDCLVP111 clock driver distributes one

differential clock pair of LVPECL input, (CLK0, CLK1)

to ten pairs of differential LVPECL clock (Q0, Q9)

outputs with minimum skew for clock distribution. The

CDCLVP111 can accept two clock sources into an

input multiplexer. The CDCLVP111 is specifically

designed for driving 50-Ω transmission lines. When

an output pin is not used, leaving it open is

recommended to reduce power consumption. If only

one of the output pins from a differential pair is used,

the other output pin must be identically terminated to

50 Ω.

The VBB reference voltage output is used if single–

ended input operation is required. In this case, the VBB pin should be connected to CLK0 and bypassed

to GND through a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP111 device is characterized for operation from –40°C to 85°C.