CDC536DB集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

CDC536DB属于集成电路（IC）的时钟发生器PLL频率合成器。由德州仪器制造生产的CDC536DB时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。

FEATURES

· Low-Output Skew for Clock-Distribution and

Clock-Generation Applications

· Operates at 3.3-V VCC

· Distributes One Clock Input to Six Outputs

· One Select Input Configures Three Outputs to

Operate at One-Half or Double the Input

Frequency

· No External RC Network Required

· External Feedback Pin (FBIN) Is Used to

Synchronize the Outputs to the Clock Input

· Application for Synchronous DRAM,

High-Speed Microprocessor

· Negative-Edge-Triggered Clear for

Half-Frequency Outputs

· TTL-Compatible Inputs and Outputs

· Outputs Drive 50-W Parallel-Terminated

Transmission Lines

· State-of-the-Art EPIC-IIB™ BiCMOS Design

Significantly Reduces Power Dissipation

· Distributed VCC and Ground Pins Reduce

Switching Noise

· Packaged in Plastic 28-Pin Shrink Small

Outline Package

DESCRIPTION

The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely

align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically

designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to

100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V

VCC and is designed to drive a 50-W transmission line.

The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock

(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between

CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input

configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed

back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty

cycle at the input clock.

Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.

When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass

the PLL. TEST should be strapped to GND for normal operation.