CDC2510C集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Use CDCVF2510A as a Replacement for

this Device

Designed to Meet PC SDRAM Registered

DIMM Design Support Document Rev. 1.2

Spread Spectrum Clock Compatible

Operating Frequency 25 MHz to 125 MHz

Static tPhase Error Distribution at 66 MHz

to 100 MHz is ±150 ps

Drop-In Replacement for TI CDC2510A With

Enhanced Performance

Jitter (cyc − cyc) at 66 MHz to 100 MHz is

|100 ps|

Available in Plastic 24-Pin TSSOP

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

Distributes One Clock Input to One Bank of

Ten Outputs

External Feedback (FBIN) Terminal Is Used

to Synchronize the Outputs to the Clock

Input

On-Chip Series Damping Resistors

No External RC Network Required

Operates at 3.3 V

description

The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL

to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC = 3.3 V . It also

provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted

to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output

enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input

is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback

signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDC2510C is characterized for operation from 0°C to 85°C.

For application information, see the High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread

Spectrum Clocking (SSC) (literature number SCAA039) application reports.