CDC111中文资料3.3V LVPECL 差动时钟驱动器数据手册TI规格书

描述 Description

The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN\\) to nine pairs of differential clock (Y, Y\\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50- transmission lines. When the output-enable (OE\\) is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE\\ is high, the nine differential outputs are in static states (Y outputs are in the low state, Y\\ outputs are in the high state). The VREF output can be strapped to the CLKIN\\ input for a single-ended CLKIN input. The CDC111 is characterized for operation from 0°C to 70°C.

特性 Features

• Low-Output Skew for Clock-Distribution Applications
• Differential Low-Voltage Pseudo-ECL (LVPECL)-Compatible Inputs and Outputs
• Distributes Differential Clock Inputs to Nine Differential Clock Outputs
• Output Reference Voltage, VREF, Allows Distribution From a Single-Ended Clock Input
• Single-Ended LVPECL-Compatible Output Enable
• Packaged in Plastic Chip Carrier