CD74HCT354E.A中文资料德州仪器数据手册PDF规格书

Features

• HC/HCT354

- Transparent Data and Select Latches

• Buffered Inputs

• Three-State Complementary Outputs

• Bus Line Driving Capability

• Typical Propagation Delay: VCC = 5V, CL = 15pF,

TA = 25oC

- Data to Output = 18ns

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Description

The CD54HC354, CD74HC354, and CD74HCT354 are data

selectors/multiplexers that select one of eight sources. In both

types, the data select bits S0, S1 and S2 are stored in

transparent latches that are enabled by a low latch enable

input, LE.

In the HC/HCT354 the data enable input, E, controls

transparent latches that pass data to the outputs when E is

high and latches in new data when E is low.

In both types the three-state outputs are controlled by three

output-enable inputs OE1, OE2, and OE3.