丝印：CD74HCT237E；Package：PDIP；High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Features • Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237 • l/O Port or Memory Selector • Two Enable Inputs to Simplify Cascading • Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25oC (CD74HC237) • Fanout (Over

文件：1.16658 Mbytes 页数：28 Pages

TI

德州仪器

3-to-8-line Decoder/Demultiplexer with Address Latch

Description The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output ena

文件：195.67 Kbytes 页数：8 Pages

RENESAS

瑞萨

3-to-8-line Decoder/Demultiplexer with Address Latch

Description The HD74HCT237 decodes a three-bit Address to one-of-eight active-high outputs. The device has a transparent latch for storage of the Address. Two Chip Selects, one active-low and one active-high, are provided to facilitate the demultiplexing, cascading, and chip-selecting functions.

文件：57.9 Kbytes 页数：8 Pages

HitachiHitachi Semiconductor

日立日立公司

3-to-8-line Decoder/Demultiplexer with Address Latch

Description The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output ena

文件：195.67 Kbytes 页数：8 Pages

RENESAS

瑞萨