CD74HCT237中文资料具有地址锁存器的高速 CMOS 逻辑 3 至 8 线路解码器/多路解复用器数据手册TI规格书

描述 Description

The CD74HC137, CD74HCT137, ’HC237, and CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic.
Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A \"Low\" LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE\\1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a \"Low\"; in the ’HC237 and CD74HCT237 the selected output is a \"High\".

特性 Features

• Select One of Eight Data Outputs
• Active High for ’HC237 and CD74HCT237
• Two Enable Inputs to Simplify Cascading
• Fanout (Over Temperature Range)
• Bus Driver Outputs. . . . 15 LSTTL Loads
• Balanced Propagation Delay and Transition Times
• HC Types
• High Noise Immunity: NIL = 30%, NIH = 30%, of VCC at VCC = 5V
• Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il 1µA at VOL, VOH
Data sheet acquired from Harris Semiconductor