CD74HCT161MT集成电路（IC）的计数器除法器规格书PDF中文资料

CD74HCT161MT属于集成电路（IC）的计数器除法器。由德州仪器制造生产的CD74HCT161MT计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。

特性 Features

• ’HC161, ’HCT161 4-Bit Binary Counter,

Asynchronous Reset

• ’HC163, ’HCT163 4-Bit Binary Counter,

Synchronous Reset

• Synchronous Counting and Loading

• Two Count Enable Inputs for n-Bit Cascading

• Look-Ahead Carry for High-Speed Counting

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

描述 Description

The ’HC161, ’HCT161, ’HC163, and ’HCT163 are

presettable synchronous counters that feature look-ahead

carry logic for use in high-speed counting applications. The

’HC161 and ’HCT161 are asynchronous reset decade and

binary counters, respectively; the ’HC163 and ’HCT163

devices are decade and binary counters, respectively, that

are reset synchronously with the clock. Counting and

parallel presetting are both accomplished synchronously

with the negative-to-positive transition of the clock.

A low level on the synchronous parallel enable input, SPE,

disables counting operation and allows data at the P0 to P3

inputs to be loaded into the counter (provided that the

setup and hold requirements for SPE are met).

All counters are reset with a low level on the Master Reset

input, MR. In the ’HC163 and ’HCT163 counters

(synchronous reset types), the requirements for setup and

hold time with respect to the clock must be met.

Two count enables, PE and TE, in each counter are

provided for n-bit cascading. In all counters reset action

occurs regardless of the level of the SPE, PE and TE inputs

(and the clock input, CP, in the ’HC161 and ’HCT161

types).

If a decade counter is preset to an illegal state or assumes

an illegal state when power is applied, it will return to the

normal sequence in one count as shown in state diagram.

The look-ahead carry feature simplifies serial cascading of

the counters. Both count enable inputs (PE and TE) must

be high to count. The TE input is gated with the Q outputs

of all four stages so that at the maximum count the terminal

count (TC) output goes high for one clock period. This TC

pulse is used to enable the next cascaded stage.