CD74HC93EE4中文资料德州仪器数据手册PDF规格书

1 Features

• Can be configured to divide by 2, 8, and 16

• Asynchronous reset

• Fanout (over temperature range)

– Standard outputs: 10 LSTTL loads

– Bus driver outputs: 15 LSTTL loads

• Wide operating temperature range: – 55°C to

125°C

• Balances propagation delay and transition times

• Signigicant power reduction compared to LSTTL

logic ICs

• HC types

– 2 V to 6 V operation

– High noise immunity: NIL = 30%, NIH = 30% of

VCC

• HCT types

– 4.5 V to 5.5 V operation

– Direct LSTTL input logic compatibility, VIL = 0.8

V (max), VIH = 2 V (min)

– CMOS input compatibility, II ≤ 1 μA at VOL, VOH

2 Description

The CD74HC93 and CD74HCT93 are high-speed

silicon-gate CMOS devices and are pin-compatible

with low power Schottky TTL (LSTTL). These 4-

bit binary ripple counters consist of four flip-flops

internally connected to provide a divide-by-two section

and a divide-by-eight section. Each section has

a separate clock input (CP0 and CP1) to initiate

state changes of the counter on the HIGH to LOW

clock transition. State changes of the Qn outputs do

not occur simultaneously because of internal ripple

delays. Therefore, decoded output signals are subject

to decoding spikes and should not be used for clocks

or strobes.