丝印：HC73M；Package：SOIC；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 页数：24 Pages

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德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes 页数：18 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：452.31 Kbytes 页数：15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes 页数：15 Pages

TI

德州仪器