CD74HC4046APWT.A中文资料德州仪器数据手册PDF规格书

特性 Features

• Operating Frequency Range

- Up to 18MHz (Typ) at VCC = 5V

- Minimum Center Frequency of 12MHz at VCC = 4.5V

• Choice of Three Phase Comparators

- EXCLUSIVE-OR

- Edge-Triggered JK Flip-Flop

- Edge-Triggered RS Flip-Flop

• Excellent VCO Frequency Linearity

• VCO-Inhibit Control for ON/OFF Keying and for Low

Standby Power Consumption

• Minimal Frequency Drift

• Operating Power Supply Voltage Range

- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V

- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Applications

• FM Modulation and Demodulation

• Frequency Synthesis and Multiplication

• Frequency Discrimination

• Tone Decoding

• Data Synchronization and Conditioning

• Voltage-to-Frequency Conversion

• Motor-Speed Control

描述 Description

The ’HC4046A and ’HCT4046A are high-speed silicon-gate

CMOS devices that are pin compatible with the CD4046B of

the “4000B” series. They are specified in compliance with

JEDEC standard number 7.

The ’HC4046A and ’HCT4046A are phase-locked-loop

circuits that contain a linear voltage-controlled oscillator

(VCO) and three different phase comparators (PC1, PC2 and

PC3). A signal input and a comparator input are common to

each comparator.

The signal input can be directly coupled to large voltage

signals, or indirectly coupled (with a series capacitor) to small

voltage signals. A self-bias input circuit keeps small voltage

signals within the linear region of the input amplifiers. With a

passive low-pass filter, the 4046A forms a second-order loop

PLL. The excellent VCO linearity is achieved by the use of

linear op-amp techniques.