CD74HC4017-EP中文资料具有 10 个解码输出的增强型产品十进制计数器/除法器数据手册TI规格书

描述 Description

The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\\ input to cascade several stages. CE\\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.

特性 Features

• Controlled Baseline
• Extended Temperature Performance of –40°C to 125°C
• Enhanced Product-Change Notification
• Fully Static Operation
• Common Reset
• Typical fmax = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25°C
• Bus Driver Outputs . . . 15 LSTTL Loads
• Significant Power Reduction Compared to LSTTL Logic ICs
• High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.