CD74HC40103QM96EP.A中文资料德州仪器数据手册PDF规格书

Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

Extended Temperature Performance of

−40°C to 125°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Enhanced Product-Change Notification

Qualification Pedigree†

Synchronous or Asynchronous Preset

Cascadable in Synchronous or Ripple

Mode

Fanout (Over Temperature Range)

− Standard Outputs . . . 10 LSTTL Loads

− Bus Driver Outputs . . . 15 LSTTL Loads

Balanced Propagation Delay and Transition

Times

Significant Power Reduction Compared to

LSTTL Logic ICs

VCC Voltage = 2 V to 6 V

High Noise Immunity NIL or NIH = 30% of

VCC, VCC = 5 V

description/ordering information

The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage

synchronous down counter with a single output, which is active when the internal count is zero. The device

contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for

clearing the counter to its maximum count, and for presetting the counter either synchronously or

asynchronously. All control inputs and the terminal count (TC) output are active-low logic.

In normal operation, the counter is decremented by one count on each positive transition of the clock (CP)

output. Counting is inhibited when the terminal enable (TE) input is high. TC goes low when the count reaches

zero, if TE is low, and remains low for one full clock period.

When the synchronous preset enable (PE) input is low, data at the P0−P7 inputs are clocked into the counter on

the next positive clock transition, regardless of the state of TE. When the asynchronous preset enable (PL) input

is low, data at the P0−P7 inputs asynchronously are forced into the counter, regardless of the state of the PE, TE,

or CP inputs. Inputs P0−P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset

(MR) input is low, the counter asynchronously is cleared to its maximum count of 25510, regardless of the state of

any other input. The precedence relationship between control inputs is indicated in the truth table.