CD74HC40103EE4中文资料德州仪器数据手册PDF规格书

Features

• Synchronous or Asynchronous Preset

• Cascadable in Synchronous or Ripple Mode

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Description

The ’HC40103 and CD74HCT40103 are manufactured with

high speed silicon gate technology and consist of an 8-stage

synchronous down counter with a single output which is

active when the internal count is zero. The 40103 contains a

single 8-bit binary counter. Each has control inputs for

enabling or disabling the clock, for clearing the counter to its

maximum count, and for presetting the counter either

synchronously or asynchronously. All control inputs and the

TC output are active-low logic.

In normal operation, the counter is decremented by one

count on each positive transition of the CLOCK (CP).

Counting is inhibited when the TE input is high. The TC

output goes low when the count reaches zero if the TE input

is low, and remains low for one full clock period.

When the PE input is low, data at the P0-P7 inputs are

clocked into the counter on the next positive clock transition

regardless of the state of the TE input. When the PL input is

low, data at the P0-P7 inputs are asynchronously forced into

the counter regardless of the state of the PE, TE, or CLOCK

inputs. Input P0-P7 represent a single 8-bit binary word for

the 40103. When the MR input is low, the counter is

asynchronously cleared to its maximum count of 25510,

regardless of the state of any other input. The precedence

relationship between control inputs is indicated in the truth

table.

If all control inputs except TE are high at the time of zero

count, the counters will jump to the maximum count, giving a

counting sequence of 10016 or 25610 clock pulses long.

The 40103 may be cascaded using the TE input and the TC

output, in either a synchronous or ripple mode. These

circuits possess the low power consumption usually

associated with CMOS circuitry, yet have speeds

comparable to low power Schottky TTL circuits and can drive

up to 10 LSTTL loads.