CD74HC191中文资料高速 CMOS 逻辑可预设的同步 4 位二进制加/减计数器数据手册TI规格书

描述 Description

The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\\ input. Counting occurs when LOAD\\ is high, count enable (CTEN)\\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\\ (see Figure 2).
If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).

特性 Features

• 2-V to 6-V VCC Operation (’HC190,191)
• 4.5-V to 5.5-V VCC Operation (’HCT191)
• Wide Operating Temperature Range of –55 to 125°C
• Synchronous Counting and Asynchronous Loading
• Two Outputs for n-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Balanced Propagation Delay and Transition Times
• Standard Outputs Drive Up To 15 LS-TTL Loads
• Significant Power Reduction Compared to LS-TTL Logic ICs

简介

CD74HC191属于集成电路（IC）的计数器除法器。由TI制造生产的CD74HC191计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。