CD74HC112PW集成电路（IC）的触发器规格书PDF中文资料

CD74HC112PW属于集成电路（IC）的触发器。由德州仪器制造生产的CD74HC112PW触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。

1 Features

• Hysteresis on clock inputs for improved noise

immunity and increased input rise and fall times

• Asynchronous set and reset

• Complementary outputs

• Buffered inputs

• Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA

= 25℃

• Fanout (over temperature range)

– Standard outputs: 10 LSTTL loads

– Bus driver outputs: 15 LSTTL loads

• Wide operating temperature range: -55℃ to 125℃

• Balanced propagation delay and transition times

• Significant power reduction compared to LSTTL

Logic ICs

• HC types

– 2 V to 6 V operation

– High noise immunity: NIL = 30, NIH = 30 of

VCC at VCC = 5 V

• HCT types

– 4.5 V to 5.5 V operation

– Direct LSTTL input logic compatibility, VIL = 0.8

V (max), VIH = 2 V (min)

– CMOS input compatibility, II ≤ 1 μA at VOL, VOH

2 Description

The ’HC112 and ’HCT112 utilize silicon-gate CMOS

technology to achieve operating speeds equivalent to

LSTTL parts. They exhibit the low power consumption

of standard CMOS integrated circuits, together with

the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, PRE, CLR,

and Clock inputs and Q and Q outputs. They

change state on the negative-going transition of

the clock pulse. PRE and CLR are accomplished

asynchronously by low-level inputs.

The HCT logic family is functionally as well as pin

compatible with the standard LS logic family.