CD74FCT273M集成电路（IC）的触发器规格书PDF中文资料

CD74FCT273M属于集成电路（IC）的触发器。由美国德州仪器公司制造生产的CD74FCT273M触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。

BiCMOS Technology With Low Quiescent

Power

Buffered Inputs

Direct Clear Input

48-mA Output Sink Current

Output Voltage Swing Limited to 3.7 V

Controlled Output Edge Rates

Input/Output Isolation From VCC

SCR Latch-Up-Resistant BiCMOS Process

and Circuit Design

Applications Include:

– Buffer/Storage Registers

– Shift Registers

– Pattern Generators

Package Options Include Plastic

Small-Outline (M) Package and Standard

Plastic (E) DIP

description

The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR) input. This device uses

a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that

limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V)

reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and

ground bounce and their effects during simultaneous output switching. The output configuration also enhances

switching speed and is capable of sinking 48 mA.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the

positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not

directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the

D input has no effect at the output. All eight flip-flops are controlled by a common clock (CLK) and a common

reset (CLR). The outputs are placed in a low state when CLR is taken low, independent of the CLK.

The CD74FCT273 is characterized for operation from 0°C to 70°C.